Fu-Liang YANG 楊富量
Director and Distinguished Research Fellow

Ways to contact me:

Fax: 02-2787-3122
Address: Research Center for Applied Sciences, Academia Sinica
128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan



Research Fields:

  • Sub-10nm CMOS Logic Device, Physics and Process Integration.
  • High Speed Low Power SRAM Cell Device, Architecture Optimization and Cell Size Minimization.
  • High Sensitivity and/or Rapid Identification with Nano Device for Bio-Sensor.
  • Integrated High Performance Energy Harvesting Chip with CMOS Device.

Recent Publications:

  1. I-Fang Cheng, Hsien-Chang Chang, Tzu-Ying Chen, Chenming Hu, and Fu-Liang Yang, “Rapid (<5min) Identification of Pathogen in Human Blood by Electrokinetic Concentration and Surface-Enhanced Raman Spectroscopy”, Scientific Reports, 6 August 2013.
  2. M.C. Chen, C.Y. Lin, B.Y. Chen, C.H. Lin, G.W. Huang, ChiaHua Ho, Tahui Wang, Chenming Hu, and F.L. Yang, “Random Telegraph Noise in 1X nm CMOS Silicide Contacts and a Method to Extract Trap Density”, IEEE Electron Device Letters (EDL) , pp.591-593, 2012.
  3. Wen-Hsien Huang, Jia-Min Shieh*, Fu-Ming Pan, Chang-Hong Shen, Yu-Chung Lien,Min-An Tsai, Hao-Chung Kuo, Bau-Tong Dai, and Fu-Liang Yang," UV–Visible Light-Trapping Structure of LooselyPacked Submicrometer Silica Sphere for Amorphous Silicon Solar Cells", IEEE Electron Device Letters(EDL), 33, 1036(2012).
  4. Yu-Chung Lien, Jia-Min Shieh*, Wen-Hsien Huang, Cheng-Hui Tu, Chieh Wang, Chang-Hong Shen, Bau-Tong Dai, Ci-Ling Pan, Chenming Hu, and Fu-Liang Yang, "Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing", APPLIED PHYSICS LETTERS 100, 143501 (2012). (Research Highlights)
  5. M.C. Chen, H.Y. Chen, C.Y. Lin, C.H. Chien, T.F. Hsieh, J.T. Horng, J.T. Qiu, C.C. Huang, C.H. Ho and F.L. Yang, ”A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications”, Sensors, pp.3952-3963, 2012.
  6. Hou-Yu Chen; Chun-Chi Chen; Fu-Kuo Hsueh; Jan-Tsai Liu; Shyi-Long Shy; Cheng-San Wu; Chao-Hsin Chien; Chenming Hu; Chien-Chao Huang; Fu-Liang Yang “A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication”, IEEE TRANSACTIONS ON ELECTRON DEVICES, V. 58-11: 3678 - 3686 NOV 2011.
  7. Chang-Hong Shen, Jia-Min Shieh, Jung Y. Huang, Hao-Chung Kuo, Chih-Wei Hsu, Bau-Tong Dai, Ching-Ting Lee, Ci-Ling Pan, and Fu-Liang Yang “Inductively coupled plasma deposited semiconductor films for low cost high-efficiency solar cells with high light-soaking stability” , APPLIED PHYSICS LETTERS, 99, 033510 (2011)
  8. Jia-Min Shieh, Wen-Chien Yu, Jung Y. Huang, Chao-Kei Wang, Bau-Tong Dai,Huang-Yan Jhan, Chih-Wei Hsu, Hao-Chung Kuo, Fu-Liang Yang, and Ci-Ling Pan ”Near-infrared silicon quantum dots metal-oxide-semiconductor field-effect transistor photodetector” APPLIED PHYSICS LETTERS 94, 241108 (2009) .
  9. Couthored a Chapter “Overview of Metal-Oxide Resistive Memory”, in “NONVOLATILE MEMORIES, Materials, Devices and Applications”, ChiaHua Ho and Fu-Liang Yang, edited by Tseung-Yuen Tseng and Simon M. Sze, AMERICAN SCIENTIFIC PUBLISHERS, 2012
  10. Guang-Li Luo, Shih-Chiang Huang, Cheng-Ting Chung, Dawei Heh1, Chao-Hsin Chien, Chao-Ching Cheng, Yao-Jen Lee, Wen-Fa Wu, Chiung-Chih Hsu, Mei-Ling Kuo, Jay-Yi Yao, Mao-Nan Chang, Chee-Wee Liu, Chenming Hu, Chun-Yen Chang, and Fu-Liang Yang, “A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage”, IEDM Dec.2009
  11. Yao-Jen Lee, Yu-Lun Lu, Fu-Kuo Hsueh, Kuo-Chin Huang, Chia-Chen Wan, Tz-Yen Cheng, Ming-Hung Han, Jeff M. Kowalski, Jeff E. Kowalski, Dawei Heh, Hsi-Ta Chuang, Yiming Li, Tien-Sheng Chao, Ching-Yi Wu, and Fu-Liang Yang, “3D 65nm CMOS with 320°C Microwave Dopant Activation”, IEDM Dec.2009
  12. Chen, HM (Chen, Hung-Ming); Hwang, JR (Hwang, Jiunn-Ren); Li, Y (Li, Yiming); Yang, FL (Yang, Fu-Liang) “Novel strained CMOS devices with STI stress buffer layers”, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Proceedings of Technical Papers Pages: 80-81 DOI: 10.1109/ISPACS.2007.4445828, published 2007
    [ DOI:10.1109/ISPACS.2007.4445828 ]
  13. Li, YM (Li, Yiming)1; Hwang, CH (Hwang, Chih-Hong)1; Yu, SM (Yu, Shao-Ming); Huang, HM (Huang, Hsuan-Ming)1; Yeh, TC (Yeh, Ta-Ching)1; Cheng, HW (Cheng, Hui-Wen)1; Chen, HM (Chen, Hung-Ming); Hwang, JR (Hwang, Jiunn-Ren); Yang, FL (Yang, Fu-Liang) “Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperature”, SISPAD 2007: SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2007(TU Wien, Vienna, AUSTRIA) Pages: 365-368 DOI: 10.1007/978-3-211-72861-1_88 Published: 2007
    [ DOI:10.1007/978-3-211-72861-1_88 ]
  14. Fu-Liang Yang, Jiunn-Ren Hwang, Hung-Ming Chen, Jeng-Jung Shen,.., and Denny D. Tang, “Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS”, Symp. VLSI Tech., 2007. (Kyoto, Japan)
  15. Dunga, MV (Dunga, Mohan V.); Lin, CH (Lin, Chung-Hsun); Lu, DD (Lu, Darsen D.); Xiong, W (Xiong, Weize); Cleavelin, CR (Cleavelin, C. R.); Patruno, P (Patruno, P.); Hwang, JR (Hwang, Jiunn-Ren); Yang, FL (Yang, Fu-Liang); Niknejad, AM (Niknejad, Ali M.); Hu, C (Hul, Chenming) “BSIM-MG: A versatile multi-gate FET model for mixed-signal design”, 2007 Symposium on VLSI Technology, (Kyoto, JAPAN) Digest of Technical Papers Pages: 60-61 DOI: 10.1109/VLSIT.2007.4339727 Published: 2007
    [ DOI:10.1109/VLSIT.2007.4339727 ]
  16. Yang, FL (Yang, Fu-Liang); Hwang, JR (Hwang, Jiunn-Ren); Li, YM (Li, Yiming) ”Electrical characteristic fluctuations in sub-45nm CMOS devices”, PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE Book Series: IEEE Custom Integrated Circuits Conference Pages: 691-694 DOI: 10.1109/CICC.2006.320881 Published: 2006
    [ DOI:10.1109/CICC.2006.320881 ]
  17. Jiunn-Ren Hwang, Tsung-Lin Lee, Huan-Chi Ma*, Tzyh-Cheang Lee,…, and Fu-Liang Yang,“20nm Gate Bulk-FinFET SONOS Flash”, IEDM, 2005. (Washington DC, USA)
  18. Hou-Yu Chen, Chang-Yun Chang, Chien-Chao Huang, T.-X. Chung, . ., and Fu-Liang Yang, “Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183m2 6T-SRAM Cell by Immersion Lithography”, Symp. VLSI Tech., 2005. (Kyoto, Japan)
  19. Fu-Liang Yang, Di.-Hong. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu,.. , and Chenming Hu , “5nm-Gate Nanowire FinFET” Symp. VLSI Tech., 2004. (Honolulo, USA)
  20. Fu-Liang Yang, Hou-Yu Chen, C.-C. Huang, T.-X. Chung, C.-Y. Chang,.., and Chenming Hu , “A 45nm Node SOI Technology with 0.296m2 6T-SRAM Cell”. Symp. VLSI Tech., 2004. (Honolulo, USA)
  21. Fu-Liang Yang, Di.-Hong. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu,.. , and Chenming Hu, “A 65nm Node Strained SOI Technology with Slim Spacer”, IEDM, 2003. (Washington DC, USA)
  22. Fu-Liang Yang, Hou-Yu Chen, C.-C. Huang, C.-H. Ge, K.-W. Su,…, and Chenming Hu, “Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65nm CMOS Scaling”, Symp. VLSI Tech., 2003. (Kyoto, Japan)
  23. Fu-Liang Yang, Hao-Yu Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang,..., and Chenming Hu, “25nm CMOS Omega FETs”, IEDM, 2002. (San Francisco, USA)
  24. Fu-Liang Yang, Haur-Ywh Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang,.., and Chenming Hu, “35nm CMOS FinFETs”, Symp. VLSI Tech., 2002. (Honolulo, USA)
  25. K. N. Yang, Yi-Lin Chan, Yu-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, and Chenming Hu, “High Performance 0.1 m PD SOI Tunneling-Biased MOSFETs (TB-MOS)”, IEDM, 2001 (Late News paper)


  1. Totally 242 patents, 135 USA patents (including authored and co-authored).